With the rapid development of integrated circuit (IC) manufacturing technology, the critical dimension (CD) of metal-oxide-semiconductor (MOS) transistors has become smaller and smaller. When the CD of the MOS transistors is continually shrunk, in order to low the parasitic capacitance of the gates of the MOS transistors and increase the device speed, metal gates have been widely used in the MOS transistors.
FIGS. 1˜7 illustrate semiconductor structures corresponding to certain stages of an existing fabrication method of PMOS transistors and NMOS transistors. As shown in FIG. 1, the method includes providing a semiconductor substrate 100 having an NMOS region I and a PMOS region II. A first dummy gate 101 and a third dummy gate 103 are formed on the semiconductor substrate 100 in the NMOS region I. Further, a second dummy gate 102 and a fourth dummy gate 104 are formed on the semiconductor substrate 100 in the PMOS region II. The CD of the first dummy gate 101 and the CD of the second dummy gate 102 are equal to or greater than 0.1 μm. The CD of the third dummy gate 103 is smaller than the CD of the first dummy gate 101. The CD of the fourth dummy gate 104 is smaller than the CD of the second dummy gate 102. The first dummy gate 101, the second dummy gate 102, the third dummy gate 103 and the fourth dummy gate 104 are all made of polysilicon.
Further, a silicon oxide layer 105 is formed on the semiconductor substrate 100, first dummy gate 101, the second dummy gate 102, the third dummy gate 103, and the fourth dummy gate 104. The top surface of the silicon oxide layer 105 levels with the top surfaces of the first dummy gate 101, the second dummy gate 102, the third dummy gate 103, and the fourth dummy gate 104.
Further, as shown FIG. 2, a patterned mask layer 106 is formed. The patterned mask layer 106 covers the silicon oxide layer 105 in the PMOS region II, the second dummy gate 102 and the fourth dummy gate 104. Then, the first dummy gate 101 and the third dummy gate 103 in the NMOS regions I are removed. Thus, a first gate trench 107 and a third gate trench 108 are formed in the silicon oxide layer 105 in the NMOS region II.
Further, as shown in FIG. 3, a first Al layer 109 is filled in the first gate trench 107 and the second gate trench 108. The first Al layer 109 also covers the patterned mask layer 106.
Further, as shown in FIG. 4, the portion of the first Al layer 109 higher than the silicon oxide layer 105, and the patterned mask layer 106 are removed by a chemical mechanical polishing (CMP) process. Thus, a first Al gate 110 is formed in the first gate trench 107; and a third Al gate 111 is formed in the third gate trench 108. The polishing slurry of the CMP process includes aluminum oxide particles.
Further, as shown in FIGS. 4˜5, the second dummy gate 102 and the fourth dummy gate 104 in the PMOS region II are removed. Correspondingly, a second gate trench 112 and a fourth gate trench 113 are formed in the silicon oxide layer 105 in the PMOS region II.
Further, as shown in FIG. 6, a second Al layer 114 is filled in the second gate trench 112 and the fourth gate trench 113. The second Al layer 114 also covers the silicon oxide layer 105, the first Al gate 110 and the second Al gate 111 in the NMOS region I.
Further, as shown in FIG. 7, the portion of the second Al layer 114 higher than the surface of the silicon oxide layer 105 is removed by a CMP process. Thus, a second Al gate 115 is formed in the second gate trench 112; and a fourth Al gate 116 is formed in the fourth gate trench 113.
However, the performance of the PMOS transistors may be unable to match the desired requirements, or even worse, they may fail. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.